As technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a thinner layer of the gate oxide having a low-dielectric-constant used in larger technology nodes.
However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, in a “gate last” fabrication process, achieving a low gate resistance for a field effect transistor (FET) is difficult because voids are generated in the metal gate electrode after metal layer deposition for gap filling of a high-aspect-ratio trench, thereby increasing the likelihood of device instability and/or device failure. As the gate length and spacing between devices decrease, these problems are exacerbated.